1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of memory cells. The present invention also relates a method of manufacturing a semiconductor device.
2. Description of the Related Art
As an example of a portable nonvolatile semiconductor memory device, U.S. Pat. No. 6,034,389 discloses a whole-erasable flash memory that erases all data stored therein collectively. The flash memory has a two-layer gate structure including a floating gate and a control gate. The control gate is disposed on the floating gate through an insulating layer. Data is written into and read from the floating gate by implanting and extracting electron. The control gate functions as a word line.
In a direction perpendicular to the word line, a bit line and a source line are arranged. The two-layer structure configurates a memory cell. The bit line is configured to read data from the memory cell. The source line is configured to drive the memory cell. A plurality of the memory cells is arranged to configurate a memory mat. In the memory mat, a plurality of the bit lines and a plurality of the source lines are alternately arranged in a direction perpendicular to a plurality of the word lines.
Data is written into the flash memory by a hot electron method. A voltage is selectively applied to the word line and the bit line of the memory cell into which the data is written. In addition, an electric current is applied to the source line of the memory cell into which the data is written. Thereby, a channel region is provided between a source and a drain, and an electron accelerated at the channel region and having a high energy is implanted into the floating gate.
The data in the flash memory is erased by a tunnel method. The electron stored in the floating gate is extracted to the source by applying a voltage to the source lines, and thereby the whole data stored in each of the memory cells coupled with the source lines is erased collectively.
In the memory mat, the memory cells are arranged vertically and horizontally. Thus, a wiring resistance is generated in the source lines in the memory mat. When the whole data is erased, an erasing voltage applied to the source line arranged at an inner portion of the memory mat is lower than an erasing voltage applied to the source line arranged at an outer portion of the memory mat due to the wiring resistance. Thus, a difference in an erasing property is generated between the inner portion and the outer portion of the memory mat, and the difference in the erasing property among the memory cells is increased. The difference in the erasing property may cause an error recognition of the data.
If a time for applying the voltage to the memory cells is increased for erasing the data stored in the memory cell arranged at the inner portion of the memory mat, an excess electron may be extracted from the floating gate of the memory cell arranged at the outer portion of the memory mat. Thus, a threshold voltage of the floating gate decreases from an initial threshold voltage, and it becomes difficult to write data into the floating gate. Therefore, it is undesirable to increase the time for applying the voltage to the source lines.